Display - cleanup and better "example"
* Moved test pattern to main program * Use the touchscreen to affect display brightness
This commit is contained in:
parent
f8a5204ded
commit
299adc5db9
6 changed files with 350 additions and 168 deletions
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@ -1,6 +1,7 @@
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PROJECT = BitBangDisplay
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PRJ_C_SRC = main.c \
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ssd1963.c
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ssd1963.c \
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xpt2046.c
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##############################################################################
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# Build global options
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@ -2,6 +2,7 @@
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#include "hal.h"
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#include "ssd1963.h"
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#include "xpt2046.h"
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// This is called when the board boots up with the user button pressed. The
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// idea is to enter this mode if the wrong SPI device has been used and flashing
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@ -16,8 +17,88 @@ static void lockdown( void )
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}
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void display_off( void );
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void display_test_pattern( u16 start_mask );
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static void displayTestPattern( u16 start_mask )
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{
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_ssd1963_clear_cs;
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ssd1963StartWriting( 0 , 0 );
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int i;
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for ( i = 0 ; i < SSD1963_SCR_HEIGHT ; i ++ ) {
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u16 j , c = start_mask;
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for ( j = 0 ; j < SSD1963_SCR_WIDTH ; j ++ ) {
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if ( ( j & 7 ) == 7 ) {
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c >>= 1;
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if ( !c ) {
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c = 0x8000;
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}
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}
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ssd1963WriteData( c );
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}
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}
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_ssd1963_set_cs;
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}
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static int tryReading;
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static void onTouchscreenIRQ( EXTDriver * driver __attribute__((unused)) ,
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expchannel_t channel __attribute__((unused)) )
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{
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tryReading = TRUE;
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}
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#define PORT(P) \
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case (int) GPIO##P : \
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port = EXT_MODE_GPIO##P; \
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break;
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static void initIRQs( void )
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{
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EXTConfig config;
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u32 i;
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for ( i = 0 ; i < EXT_MAX_CHANNELS ; i ++ ) {
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if ( i == XPT2046_IRQ_PAD ) {
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int port;
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switch ( (int) XPT2046_IRQ_PORT ) {
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default: PORT(A); PORT(B);
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PORT(C); PORT(D); PORT(E);
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PORT(F); PORT(G); PORT(H);
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}
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config.channels[ i ].mode = EXT_CH_MODE_FALLING_EDGE
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| EXT_CH_MODE_AUTOSTART | port;
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config.channels[ i ].cb = &onTouchscreenIRQ;
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} else {
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config.channels[ i ].mode = EXT_CH_MODE_DISABLED;
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config.channels[ i ].cb = NULL;
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}
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}
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extStart( &EXTD1 , &config );
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}
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static void checkTouchScreen( void )
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{
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int x , y;
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if ( ! xpt2046GetAverageCoordinates( &x , &y , 3 ) ) {
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return;
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}
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x >>= 8;
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_ssd1963_clear_cs;
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ssd1963WriteCommand( SSD1963_CMD_SET_POST_PROC );
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ssd1963WriteData( 0x40 );
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ssd1963WriteData( x );
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ssd1963WriteData( 0x40 );
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if ( y > 2048 ) {
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ssd1963WriteData( 0 );
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} else {
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ssd1963WriteData( 1 );
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}
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_ssd1963_set_cs;
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}
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int main( void )
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{
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@ -27,14 +108,18 @@ int main( void )
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lockdown( );
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}
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xpt2046Init( );
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initIRQs();
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ssd1963Init( );
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int i = 0;
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while (TRUE) {
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display_test_pattern( 1 << i );
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displayTestPattern( 1 << i );
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chThdSleep(100);
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i = ( i + 1 ) % 16;
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if ( palReadPad( GPIOA , GPIOA_BUTTON ) ) {
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display_off( );
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if ( tryReading ) {
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checkTouchScreen( );
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tryReading = FALSE;
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}
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}
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}
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@ -4,66 +4,43 @@
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#include "ssd1963.h"
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#define _command 0x40
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#define _delay 0x80
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#define _ndata(x) ( (u8)( (x) & 0x3f) )
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static const u8 _ssd1963_reset_sequence[ ] = {
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/*
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* PLL configuration
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* -----------------
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*
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* PLL = input * ( P1 + 1 ) / ( P2 + 1 )
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* (P1 : 8 bits ; P2 : 4 bits; P3 : junk)
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*
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* 1/ The ITDB02-4.3 board has a 12MHz crystal (which contradicts the
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* SSD1963 datasheet - wtf?).
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* 2/ The SSD1963 must be clocked at *at most* 110MHz.
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* 3/ Also, 250MHz < input * ( P1 + 1 ) < 800MHz
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* 4/ The STM32F4 can communicate at 50MHz.
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* 5/ The SSD1963 accepts PLL/2 accesses per second.
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*
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* 100MHz = 12MHz * ( P1 + 1 ) / ( P2 + 1 )
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* => P1 = 49, P2 = 5
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* 100MHz = 10MHz * ( P1 + 1 ) / ( P2 + 1 )
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* => P1 = 19, P2 = 1
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*/
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_command | _ndata(3) ,
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// PLL configuration
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SSD1963_COMMAND | SSD1963_DATA(3) ,
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SSD1963_CMD_SET_PLL_MN ,
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0x31 , 0x05 , 0x04 ,
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// 0x1e , 0x02 , 0x04 ,
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0x1e , 0x02 , 0x04 ,
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// Enable PLL and wait until it's stable
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_command | _delay | _ndata(1) ,
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SSD1963_COMMAND | SSD1963_DELAY | SSD1963_DATA(1) ,
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SSD1963_CMD_SET_PLL , 1 ,
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1 ,
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// Fully enable PLL
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_command | _ndata(1) ,
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SSD1963_COMMAND | SSD1963_DATA(1) ,
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SSD1963_CMD_SET_PLL , 3 ,
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};
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static const u8 _ssd1963_init_sequence[ ] = {
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// Software reset
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_command | _delay ,
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SSD1963_COMMAND | SSD1963_DELAY ,
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SSD1963_CMD_SOFT_RESET ,
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5 ,
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/* Pixel clock: screw finesse, crank that up to the max */
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_command | _ndata( 3 ) | _delay ,
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// Pixel clock: screw finesse, crank that up to the max
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SSD1963_COMMAND | SSD1963_DATA( 3 ) | SSD1963_DELAY ,
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SSD1963_CMD_SET_LSHIFT_FREQ ,
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0x07 , 0xff , 0xff ,
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15 ,
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// Use 565 RGB format
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_command | _delay | _ndata(1) ,
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SSD1963_COMMAND | SSD1963_DELAY | SSD1963_DATA(1) ,
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SSD1963_CMD_SET_PIXEL_FORMAT ,
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0x03 ,
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5 ,
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// Setup LCD panel
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_command | _ndata( 7 ) ,
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SSD1963_COMMAND | SSD1963_DATA( 7 ) ,
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SSD1963_CMD_SET_LCD_MODE ,
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0x20 , // Data width 24-bit, FRC and dithering disabled
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// Data latch on falling edge
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@ -78,7 +55,7 @@ static const u8 _ssd1963_init_sequence[ ] = {
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( ( SSD1963_SCR_HEIGHT - 1 ) & 0xff ) ,
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0x00 , // Ignored (serial interface)
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_command | _ndata( 8 ) ,
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SSD1963_COMMAND | SSD1963_DATA( 8 ) ,
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SSD1963_CMD_SET_HORI_PERIOD ,
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0x02 , 0x13 , // Total period (PCLK)
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0x00 , 0x08 , // Non-display period
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@ -86,86 +63,35 @@ static const u8 _ssd1963_init_sequence[ ] = {
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0x00 , 0x02 , // Start location (PCLK)
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0x00 , // Ignored (serial interfaces)
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_command | _ndata( 7 ) ,
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SSD1963_COMMAND | SSD1963_DATA( 7 ) ,
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SSD1963_CMD_SET_VERT_PERIOD ,
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0x01 , 0x20 , // Vertical total period
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0x00 , 0x04 , // Non-display period
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0x0c , // Sync pulse width
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0x00 , 0x02 , // Start location
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_command | _ndata(1) ,
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0x36 ,
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0x00 ,
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SSD1963_COMMAND | SSD1963_DATA(1) ,
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SSD1963_CMD_SET_ADDRESS_MODE ,
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0x00 , // Top to bottom, left to right, no reversing,
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// RGB framebuffer, LCD l-to-r refresh, no
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// flipping
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_command ,
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// TE signal is not connected on the ITDB02-4.3
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SSD1963_COMMAND ,
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SSD1963_CMD_SET_TEAR_OFF ,
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// Set standard gamma curve
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SSD1963_COMMAND | SSD1963_DATA(1) ,
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SSD1963_CMD_SET_GAMMA_CURVE ,
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1 ,
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// Enable display
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SSD1963_COMMAND ,
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SSD1963_CMD_SET_DISPLAY_ON ,
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_command | _ndata(6) ,
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SSD1963_CMD_SET_PWM_CONF ,
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0x06 , 0xf0 , 0x01 , 0xf0 , 0 , 0 ,
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_command | _ndata(1) ,
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0xd0 ,
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0x0d ,
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_command | _ndata(1) , SSD1963_CMD_SET_GAMMA_CURVE, 1 ,
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//_command | SSD1963_CMD_ENTER_NORMAL_MODE ,
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//_command | SSD1963_CMD_EXIT_INVERT_MODE ,
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_command , SSD1963_CMD_EXIT_IDLE_MODE ,
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/*
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SSD1963_CMD_SET_TEAR_OFF ,
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*/
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};
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#define _ssd1963_wcmd(command) \
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do { \
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_ssd1963_clear_rs; \
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_ssd1963_write( command ); \
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_ssd1963_clear_wr; \
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_ssd1963_set_wr; \
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} while ( FALSE )
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#define _ssd1963_wdata(data) \
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do { \
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_ssd1963_set_rs; \
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_ssd1963_write( data ); \
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_ssd1963_clear_wr; \
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_ssd1963_set_wr; \
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} while ( FALSE )
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void _ssd1963_run_sequence( const u8 * sequence , u32 size )
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{
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_ssd1963_clear_cs;
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u32 addr = 0;
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u8 has_command = 0 , has_data = 0 , has_delay = 0;
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while ( addr < size ) {
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if ( has_command ) {
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u16 command = sequence[ addr ++ ];
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_ssd1963_wcmd( command );
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has_command = 0;
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} else if ( has_data ) {
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u16 data = sequence[ addr ++ ];
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_ssd1963_wdata( data );
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has_data --;
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} else if ( has_delay ) {
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u8 delay = sequence[ addr ++ ];
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chThdSleep( delay );
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has_delay = 0;
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} else {
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u8 value = sequence[ addr ++ ];
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has_command = ( ( value & _command ) == _command );
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has_delay = ( ( value & _delay ) == _delay );
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has_data = value & ~( _command | _delay );
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}
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}
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_ssd1963_set_cs;
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}
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void _ssd1963_reset_chip( void )
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static void _ssd1963_reset_chip( void )
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{
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// Select and reset the chip
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_ssd1963_set_reset;
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@ -178,29 +104,12 @@ void _ssd1963_reset_chip( void )
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chThdSleep( 100 );
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// Run the PLL init sequence
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_ssd1963_run_sequence( _ssd1963_reset_sequence ,
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ssd1963RunSequence( _ssd1963_reset_sequence ,
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sizeof( _ssd1963_reset_sequence ) );
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}
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void _ssd1963_set_pos( u32 x , u32 y )
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{
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_ssd1963_wcmd( 0x2a );
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_ssd1963_wdata( x >> 8 );
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_ssd1963_wdata( x & 0xff );
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_ssd1963_wdata( ( ( SSD1963_SCR_WIDTH - 1 ) >> 8 ) & 0xff );
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_ssd1963_wdata( ( SSD1963_SCR_WIDTH - 1 ) & 0xff );
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_ssd1963_wcmd( 0x2b );
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_ssd1963_wdata( y >> 8 );
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_ssd1963_wdata( y & 0xff );
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_ssd1963_wdata( ( ( SSD1963_SCR_HEIGHT - 1 ) >> 8 ) & 0xff );
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_ssd1963_wdata( ( SSD1963_SCR_HEIGHT - 1 ) & 0xff );
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_ssd1963_wcmd( 0x2c );
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}
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void ssd1963Init( void )
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{
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_ssd1963_init_gpio( PAL_STM32_OSPEED_LOWEST );
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@ -209,58 +118,63 @@ void ssd1963Init( void )
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chThdSleep( 10 );
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_ssd1963_init_gpio( PAL_STM32_OSPEED_HIGHEST );
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_ssd1963_run_sequence( _ssd1963_init_sequence ,
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ssd1963RunSequence( _ssd1963_init_sequence ,
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sizeof( _ssd1963_init_sequence ) );
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_ssd1963_clear_cs;
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_ssd1963_set_pos( 0 , 0 );
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ssd1963StartWriting( 0 , 0 );
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int i;
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for ( i = 0 ; i < SSD1963_SCR_HEIGHT ; i ++ ) {
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u16 j , c = 0x8000;
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for ( j = 0 ; j < SSD1963_SCR_WIDTH ; j ++ ) {
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if ( ( j & 7 ) == 7 ) {
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c >>= 1;
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if ( !c ) {
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c = 0x8000;
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}
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}
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_ssd1963_wdata( c );
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}
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for ( i = 0 ; i < SSD1963_SCR_HEIGHT * SSD1963_SCR_WIDTH ; i ++ ) {
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ssd1963WriteData( 0 );
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}
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_ssd1963_set_cs;
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}
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void display_test_pattern( u16 start_mask )
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void ssd1963RunSequence( const u8 * sequence , u32 size )
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{
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_ssd1963_clear_cs;
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_ssd1963_set_pos( 0 , 0 );
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int i;
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for ( i = 0 ; i < SSD1963_SCR_HEIGHT ; i ++ ) {
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u16 j , c = start_mask;
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for ( j = 0 ; j < SSD1963_SCR_WIDTH ; j ++ ) {
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if ( ( j & 7 ) == 7 ) {
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c >>= 1;
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if ( !c ) {
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c = 0x8000;
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}
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}
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_ssd1963_wdata( c );
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u32 addr = 0;
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u8 has_command = 0 , has_data = 0 , has_delay = 0;
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while ( addr < size ) {
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if ( has_command ) {
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u16 command = sequence[ addr ++ ];
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ssd1963WriteCommand( command );
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has_command = 0;
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} else if ( has_data ) {
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u16 data = sequence[ addr ++ ];
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ssd1963WriteData( data );
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has_data --;
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} else if ( has_delay ) {
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u8 delay = sequence[ addr ++ ];
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chThdSleep( delay );
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has_delay = 0;
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} else {
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u8 value = sequence[ addr ++ ];
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has_command = ( ( value & SSD1963_COMMAND )
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== SSD1963_COMMAND );
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has_delay = ( ( value & SSD1963_DELAY )
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== SSD1963_DELAY );
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has_data = value & ~( SSD1963_COMMAND | SSD1963_DELAY );
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}
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}
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_ssd1963_set_cs;
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}
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void display_off( void )
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void ssd1963StartWriting( u32 x , u32 y )
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{
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static int display = 1;
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display = !display;
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_ssd1963_clear_cs;
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if ( display ) {
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_ssd1963_wcmd( SSD1963_CMD_SET_DISPLAY_ON );
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} else {
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_ssd1963_wcmd( SSD1963_CMD_SET_DISPLAY_OFF );
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}
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_ssd1963_set_cs;
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ssd1963WriteCommand( 0x2a );
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ssd1963WriteData( x >> 8 );
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ssd1963WriteData( x & 0xff );
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ssd1963WriteData( ( ( SSD1963_SCR_WIDTH - 1 ) >> 8 ) & 0xff );
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ssd1963WriteData( ( SSD1963_SCR_WIDTH - 1 ) & 0xff );
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ssd1963WriteCommand( 0x2b );
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ssd1963WriteData( y >> 8 );
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ssd1963WriteData( y & 0xff );
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ssd1963WriteData( ( ( SSD1963_SCR_HEIGHT - 1 ) >> 8 ) & 0xff );
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ssd1963WriteData( ( SSD1963_SCR_HEIGHT - 1 ) & 0xff );
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ssd1963WriteCommand( 0x2c );
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}
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@ -21,6 +21,7 @@
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#define SSD1963_CMD_SET_DISPLAY_OFF 0x28
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#define SSD1963_CMD_SET_DISPLAY_ON 0x29
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#define SSD1963_CMD_SET_TEAR_OFF 0x34
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#define SSD1963_CMD_SET_ADDRESS_MODE 0x36
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#define SSD1963_CMD_EXIT_IDLE_MODE 0x38
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#define SSD1963_CMD_SET_LCD_MODE 0xb0
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#define SSD1963_CMD_SET_HORI_PERIOD 0xb4
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@ -34,15 +35,40 @@
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#define SSD1963_CMD_SET_PIXEL_FORMAT 0xf0
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// Control and data ports
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#define ssd1963Ctrl (*((__IO u16 *) 0x60000000))
|
||||
#define ssd1963Data (*((__IO u16 *) 0x60020000))
|
||||
|
||||
// Command sequences
|
||||
#define SSD1963_DATA(x) ( (u8)( (x) & 0x3f) )
|
||||
#define SSD1963_COMMAND 0x40
|
||||
#define SSD1963_DELAY 0x80
|
||||
|
||||
|
||||
// Initialise the display controller
|
||||
void ssd1963Init( void );
|
||||
|
||||
// Execute a sequence of commands from the specified address
|
||||
void ssd1963RunSequence( const u8 * sequence , u32 size );
|
||||
|
||||
|
||||
// Write a command to the SSD1963
|
||||
#define ssd1963WriteCommand(command) \
|
||||
do { \
|
||||
_ssd1963_clear_rs; \
|
||||
_ssd1963_write( command ); \
|
||||
_ssd1963_clear_wr; \
|
||||
_ssd1963_set_wr; \
|
||||
} while ( FALSE )
|
||||
|
||||
// Write data to the SSD1963
|
||||
#define ssd1963WriteData(data) \
|
||||
do { \
|
||||
_ssd1963_set_rs; \
|
||||
_ssd1963_write( data ); \
|
||||
_ssd1963_clear_wr; \
|
||||
_ssd1963_set_wr; \
|
||||
} while ( FALSE )
|
||||
|
||||
|
||||
// Start writing data at the specified location
|
||||
void ssd1963StartWriting( u32 x , u32 y );
|
||||
|
||||
|
||||
#endif // _H_SSD1963_STM32F4
|
||||
|
|
|
|||
125
07-BitBangDisplay/xpt2046.c
Normal file
125
07-BitBangDisplay/xpt2046.c
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
#include "xpt2046.h"
|
||||
|
||||
static const SPIConfig _xpt2046_spi_config = {
|
||||
NULL ,
|
||||
XPT2046_NSS_PORT ,
|
||||
XPT2046_NSS_PAD ,
|
||||
SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0
|
||||
};
|
||||
|
||||
|
||||
|
||||
u16 _xpt2046_get_reading( u8 control )
|
||||
{
|
||||
u8 tData[3] = { control , 0 , 0 };
|
||||
u8 rData[3] = { 0 , 0 , 0 };
|
||||
|
||||
#if SPI_USE_MUTUAL_EXCLUSION
|
||||
spiAcquireBus( &( XPT2046_SPI_DRIVER ) );
|
||||
#endif
|
||||
|
||||
palClearPad( XPT2046_NSS_PORT , XPT2046_NSS_PAD );
|
||||
spiExchange( &( XPT2046_SPI_DRIVER ) , 3 , tData , rData );
|
||||
palSetPad( XPT2046_NSS_PORT , XPT2046_NSS_PAD );
|
||||
|
||||
#if SPI_USE_MUTUAL_EXCLUSION
|
||||
spiReleaseBus( &( XPT2046_SPI_DRIVER ) );
|
||||
#endif
|
||||
|
||||
if ( ( control & 0x08 ) == 0 ) {
|
||||
return ( rData[1] << 5 ) | ( rData[2] >> 3 );
|
||||
}
|
||||
return ( rData[1] << 4 ) | ( rData[2] >> 4 );
|
||||
}
|
||||
|
||||
|
||||
|
||||
void xpt2046Init( void )
|
||||
{
|
||||
// Initialise SPI
|
||||
spiStart( &( XPT2046_SPI_DRIVER ) , &_xpt2046_spi_config );
|
||||
|
||||
// NSS signal
|
||||
palSetPadMode( XPT2046_NSS_PORT , XPT2046_NSS_PAD ,
|
||||
PAL_MODE_OUTPUT_PUSHPULL );
|
||||
palSetPad( XPT2046_NSS_PORT , XPT2046_NSS_PAD );
|
||||
|
||||
// Main SPI signals
|
||||
palSetPadMode( XPT2046_CLK_PORT , XPT2046_CLK_PAD ,
|
||||
PAL_MODE_ALTERNATE( 5 ) );
|
||||
palSetPadMode( XPT2046_DIN_PORT , XPT2046_DIN_PAD ,
|
||||
PAL_MODE_ALTERNATE( 5 ) );
|
||||
palSetPadMode( XPT2046_DOUT_PORT , XPT2046_DOUT_PAD ,
|
||||
PAL_MODE_ALTERNATE( 5 ) );
|
||||
|
||||
// PENIRQ signal
|
||||
palSetPadMode( XPT2046_IRQ_PORT , XPT2046_IRQ_PAD , PAL_MODE_INPUT );
|
||||
|
||||
// Read a sample, leaving PENIRQ active
|
||||
_xpt2046_get_reading( 0x90 );
|
||||
}
|
||||
|
||||
|
||||
int xpt2046GetCoordinates( int * pX , int * pY )
|
||||
{
|
||||
int i;
|
||||
int allX[ 7 ] , allY[ 7 ];
|
||||
_xpt2046_get_reading( 0xd1 );
|
||||
_xpt2046_get_reading( 0x91 );
|
||||
for ( i = 0 ; i < 7 ; i ++ ) {
|
||||
allX[ i ] = _xpt2046_get_reading( 0xd1 );
|
||||
allY[ i ] = _xpt2046_get_reading( 0x91 );
|
||||
}
|
||||
|
||||
int j;
|
||||
for ( i = 0 ; i < 4 ; i ++ ) {
|
||||
for ( j = i ; j < 7 ; j ++ ) {
|
||||
int temp = allX[ i ];
|
||||
if ( temp > allX[ j ] ) {
|
||||
allX[ i ] = allX[ j ];
|
||||
allX[ j ] = temp;
|
||||
}
|
||||
temp = allY[ i ];
|
||||
if ( temp > allY[ j ] ) {
|
||||
allY[ i ] = allY[ j ];
|
||||
allY[ j ] = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
_xpt2046_get_reading( 0x90 );
|
||||
|
||||
if ( palReadPad( XPT2046_IRQ_PORT , XPT2046_IRQ_PAD ) ) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
*pX = allX[ 3 ];
|
||||
*pY = allY[ 3 ];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int xpt2046GetAverageCoordinates( int * pX , int * pY , int nSamples )
|
||||
{
|
||||
int nRead = 0;
|
||||
int xAcc = 0 , yAcc = 0;
|
||||
int x , y;
|
||||
|
||||
while ( nRead < nSamples ) {
|
||||
if ( !xpt2046GetCoordinates( &x , &y ) ) {
|
||||
break;
|
||||
}
|
||||
xAcc += x;
|
||||
yAcc += y;
|
||||
nRead ++;
|
||||
}
|
||||
|
||||
if ( nRead == 0 ) {
|
||||
return 0;
|
||||
}
|
||||
*pX = xAcc / nRead;
|
||||
*pY = yAcc / nRead;
|
||||
return 1;
|
||||
}
|
||||
31
07-BitBangDisplay/xpt2046.h
Normal file
31
07-BitBangDisplay/xpt2046.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
#ifndef _H_XPT2046_STM32F4
|
||||
#define _H_XPT2046_STM32F4
|
||||
|
||||
|
||||
// Ports and controllers for the various touchscreen pins
|
||||
// IRQ (any port will do)
|
||||
#define XPT2046_IRQ_PORT GPIOC
|
||||
#define XPT2046_IRQ_PAD 4
|
||||
// NSS (any port will do, this is done manually)
|
||||
#define XPT2046_NSS_PORT GPIOA
|
||||
#define XPT2046_NSS_PAD 4
|
||||
// CLK (must be a SPI clock port)
|
||||
#define XPT2046_CLK_PORT GPIOA
|
||||
#define XPT2046_CLK_PAD 5
|
||||
// DIN (must be a SPI MOSI port)
|
||||
#define XPT2046_DIN_PORT GPIOA
|
||||
#define XPT2046_DIN_PAD 7
|
||||
// DOUT (must be a SPI MISO port)
|
||||
#define XPT2046_DOUT_PORT GPIOA
|
||||
#define XPT2046_DOUT_PAD 6
|
||||
|
||||
// SPI driver to use
|
||||
#define XPT2046_SPI_DRIVER SPID1
|
||||
|
||||
|
||||
void xpt2046Init( void );
|
||||
int xpt2046GetCoordinates( int * pX , int * pY );
|
||||
int xpt2046GetAverageCoordinates( int * pX , int * pY , int nSamples );
|
||||
|
||||
|
||||
#endif //_H_XPT2046_STM32F4
|
||||
Loading…
Reference in a new issue