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Added (non-functional) CS43L22 code

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I just can't figure out what's wrong with it.
This commit is contained in:
Emmanuel BENOîT 2012-11-13 18:39:13 +01:00
parent b97b338d6f
commit 017631b168
13 changed files with 18801 additions and 0 deletions
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223
09-PlaySound/Makefile Normal file
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PROJECT = PlaySound
PRJ_C_SRC = main.c \
sound.c \
serial_output.c \
../ChibiOS/os/various/chprintf.c
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Enables the use of FPU on Cortex-M4.
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FPU),)
USE_FPU = no
endif
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Imported source files and paths
CHIBIOS = ../ChibiOS
include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(PRJ_C_SRC)
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(CHIBIOS)/os/various/devices_lib/accel \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of default section
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =
# List all default directories to look for include files here
DINCDIR =
# List the default directory to look for the libraries here
DLIBDIR =
# List all default libraries here
DLIBS =
#
# End of default section
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
ifeq ($(USE_FPU),yes)
USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
DDEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
endif
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
INCDIR += $(STM32INC)
USE_OPT += -DUSE_STDPERIPH_DRIVER
endif
include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

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09-PlaySound/chconf.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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#ifndef __H_CS43L22
#define __H_CS43L22
/* Chip I.D. and revision register */
#define CS43L22_REG_GET_ID 0x01
/* Chip I.D. and revision register - Chip identifier */
#define CS43L22_CHIP_ID_MASK ((uint8_t)0xf8)
/* Chip I.D. and revision register - CS43L22 identifier */
#define CS43L22_CHIP_ID ((uint8_t)0xe0)
/* Chip I.D. and revision register - Revision level - Mask */
#define CS43L22_CHIP_REV_MASK ((uint8_t)0x07)
/* Chip I.D. and revision register - Revision level - A1 */
#define CS43L22_CHIP_REV_A1 ((uint8_t)0x01)
/* Chip I.D. and revision register - Revision level - B1 */
#define CS43L22_CHIP_REV_B1 ((uint8_t)0x03)
/* Chip I.D. and revision register - Revision level - A0 */
#define CS43L22_CHIP_REV_A0 ((uint8_t)0x00)
/* Chip I.D. and revision register - Revision level - B0 */
#define CS43L22_CHIP_REV_B0 ((uint8_t)0x02)
/* Power control 1 */
#define CS43L22_REG_PWR_CTL1 0x02
/* Power control 1 - Power up */
#define CS43L22_PWR1_UP ((uint8_t)0x9e)
/* Power control 1 - Power down */
#define CS43L22_PWR1_DOWN ((uint8_t)0x01)
/* Power control 2 */
#define CS43L22_REG_PWR_CTL2 0x04
/* Power control 2 - Speaker A - Mask */
#define CS43L22_PWR2_SPKA_MASK ((uint8_t)0x03)
/* Power control 2 - Speaker A - Enabled if switch high */
#define CS43L22_PWR2_SPKA_SWHI ((uint8_t)0x01)
/* Power control 2 - Speaker A - Disabled */
#define CS43L22_PWR2_SPKA_OFF ((uint8_t)0x03)
/* Power control 2 - Speaker A - Enabled if switch low */
#define CS43L22_PWR2_SPKA_SWLO ((uint8_t)0x00)
/* Power control 2 - Speaker A - Enabled */
#define CS43L22_PWR2_SPKA_ON ((uint8_t)0x02)
/* Power control 2 - Speaker B - Mask */
#define CS43L22_PWR2_SPKB_MASK ((uint8_t)0x0c)
/* Power control 2 - Speaker B - Enabled */
#define CS43L22_PWR2_SPKB_ON ((uint8_t)0x08)
/* Power control 2 - Speaker B - Enabled if switch high */
#define CS43L22_PWR2_SPKB_SWHI ((uint8_t)0x04)
/* Power control 2 - Speaker B - Enabled if switch low */
#define CS43L22_PWR2_SPKB_SWLO ((uint8_t)0x00)
/* Power control 2 - Speaker B - Disabled */
#define CS43L22_PWR2_SPKB_OFF ((uint8_t)0x0c)
/* Power control 2 - Headphone A - Mask */
#define CS43L22_PWR2_HDA_MASK ((uint8_t)0x30)
/* Power control 2 - Headphone A - Enabled */
#define CS43L22_PWR2_HDA_ON ((uint8_t)0x20)
/* Power control 2 - Headphone A - Enabled if switch low */
#define CS43L22_PWR2_HDA_SWLO ((uint8_t)0x00)
/* Power control 2 - Headphone A - Enabled if switch high */
#define CS43L22_PWR2_HDA_SWHI ((uint8_t)0x10)
/* Power control 2 - Headphone A - Disabled */
#define CS43L22_PWR2_HDA_OFF ((uint8_t)0x30)
/* Power control 2 - Headphone B - Mask */
#define CS43L22_PWR2_HDB_MASK ((uint8_t)0xc0)
/* Power control 2 - Headphone B - Enabled */
#define CS43L22_PWR2_HDB_ON ((uint8_t)0x80)
/* Power control 2 - Headphone B - Enabled if switch high */
#define CS43L22_PWR2_HDB_SWHI ((uint8_t)0x40)
/* Power control 2 - Headphone B - Enabled if switch low */
#define CS43L22_PWR2_HDB_SWLO ((uint8_t)0x00)
/* Power control 2 - Headphone B - Disabled */
#define CS43L22_PWR2_HDB_OFF ((uint8_t)0xc0)
/* Clocking control */
#define CS43L22_REG_CLOCK_CTL 0x05
/* Clocking control - Autodetection - Enabled */
#define CS43L22_CLK_AUTO_ON ((uint8_t)0x80)
/* Clocking control - Autodetection - Disabled */
#define CS43L22_CLK_AUTO_OFF ((uint8_t)0x00)
/* Clocking control - Speed mode - Mask */
#define CS43L22_CLK_SPD_MASK ((uint8_t)0x60)
/* Clocking control - Speed mode - Single speed */
#define CS43L22_CLK_SPD_SSM ((uint8_t)0x20)
/* Clocking control - Speed mode - Half speed */
#define CS43L22_CLK_SPD_HSM ((uint8_t)0x40)
/* Clocking control - Speed mode - Double speed */
#define CS43L22_CLK_SPD_DSM ((uint8_t)0x00)
/* Clocking control - Speed mode - Quarter speed */
#define CS43L22_CLK_SPD_QSM ((uint8_t)0x60)
/* Clocking control - 32KHz group - Disabled */
#define CS43L22_CLK_32K_OFF ((uint8_t)0x00)
/* Clocking control - 32KHz group - Enabled */
#define CS43L22_CLK_32K_ON ((uint8_t)0x10)
/* Clocking control - 27MHz video clock - Enabled */
#define CS43L22_CLK_VC_ON ((uint8_t)0x08)
/* Clocking control - 27MHz video clock - Disabled */
#define CS43L22_CLK_VC_OFF ((uint8_t)0x00)
/* Clocking control - Internal MCLK/LRCK ratio - Mask */
#define CS43L22_CLK_MLR_MASK ((uint8_t)0x06)
/* Clocking control - Internal MCLK/LRCK ratio - 68 */
#define CS43L22_CLK_MLR_68 ((uint8_t)0x06)
/* Clocking control - Internal MCLK/LRCK ratio - 66 */
#define CS43L22_CLK_MLR_66 ((uint8_t)0x04)
/* Clocking control - Internal MCLK/LRCK ratio - 64 */
#define CS43L22_CLK_MLR_64 ((uint8_t)0x00)
/* Clocking control - Internal MCLK/LRCK ratio - 62 */
#define CS43L22_CLK_MLR_62 ((uint8_t)0x02)
/* Clocking control - Master clock /= 2 - Enabled */
#define CS43L22_CLK_MCDIV_ON ((uint8_t)0x01)
/* Clocking control - Master clock /= 2 - Disabled */
#define CS43L22_CLK_MCDIV_OFF ((uint8_t)0x00)
/* Interface control 1 */
#define CS43L22_REG_INT_CTL1 0x06
/* Interface control 1 - Slave mode */
#define CS43L22_IC1_SLAVE ((uint8_t)0x00)
/* Interface control 1 - Master mode */
#define CS43L22_IC1_MASTER ((uint8_t)0x80)
/* Interface control 1 - SCLK inverted polarity - Enabled */
#define CS43L22_IC1_SCPOL_ON ((uint8_t)0x40)
/* Interface control 1 - SCLK inverted polarity - Disabled */
#define CS43L22_IC1_SCPOL_OFF ((uint8_t)0x00)
/* Interface control 1 - DSP - Disabled */
#define CS43L22_IC1_DSP_OFF ((uint8_t)0x00)
/* Interface control 1 - DSP - Enabled */
#define CS43L22_IC1_DSP_ON ((uint8_t)0x10)
/* Interface control 1 - DAC interface format - Right-justified */
#define CS43L22_IC1_DIF_RJ ((uint8_t)0x08)
/* Interface control 1 - DAC interface format - I2S, up to 24 bits */
#define CS43L22_IC1_DIF_I2S ((uint8_t)0x04)
/* Interface control 1 - DAC interface format - Left-justified, up to 24 bits */
#define CS43L22_IC1_DIF_LJ ((uint8_t)0x00)
/* Interface control 1 - Audio word length - 24-bit (DSP), 20-bit (RJ) */
#define CS43L22_IC1_AWL_24 ((uint8_t)0x01)
/* Interface control 1 - Audio word length - 16-bit (DSP), 16-bit (RJ) */
#define CS43L22_IC1_AWL_16 ((uint8_t)0x03)
/* Interface control 1 - Audio word length - 32-bit (DSP), 24-bit (RJ) */
#define CS43L22_IC1_AWL_32 ((uint8_t)0x00)
/* Interface control 1 - Audio word length - 20-bit (DSP), 18-bit (RJ) */
#define CS43L22_IC1_AWL_20 ((uint8_t)0x02)
/* Interface control 2 */
#define CS43L22_REG_INT_CTL2 0x07
/* Interface control 2 - SCLK = MCLK? - Equal */
#define CS43L22_IC2_SEM_ON ((uint8_t)0x40)
/* Interface control 2 - SCLK = MCLK? - Derived */
#define CS43L22_IC2_SEM_OFF ((uint8_t)0x00)
/* Interface control 2 - Speaker/Headphone switch invert - Enabled */
#define CS43L22_IC2_SHSI_ON ((uint8_t)0x08)
/* Interface control 2 - Speaker/Headphone switch invert - Disabled */
#define CS43L22_IC2_SHSI_OFF ((uint8_t)0x00)
/* Passthrough A select */
#define CS43L22_REG_PSELA 0x08
/* Passthrough A select - Mask */
#define CS43L22_PSELA_MASK ((uint8_t)0x0f)
/* Passthrough A select - AIN4 */
#define CS43L22_PSELA_AIN4 ((uint8_t)0x08)
/* Passthrough A select - AIN3 */
#define CS43L22_PSELA_AIN3 ((uint8_t)0x04)
/* Passthrough A select - AIN1 */
#define CS43L22_PSELA_AIN1 ((uint8_t)0x01)
/* Passthrough A select - NONE */
#define CS43L22_PSELA_NONE ((uint8_t)0x00)
/* Passthrough A select - AIN2 */
#define CS43L22_PSELA_AIN2 ((uint8_t)0x02)
/* Passthrough B select */
#define CS43L22_REG_PSELB 0x09
/* Passthrough B select - Mask */
#define CS43L22_PSELB_MASK ((uint8_t)0x0f)
/* Passthrough B select - AIN4 */
#define CS43L22_PSELB_AIN4 ((uint8_t)0x08)
/* Passthrough B select - AIN3 */
#define CS43L22_PSELB_AIN3 ((uint8_t)0x04)
/* Passthrough B select - AIN1 */
#define CS43L22_PSELB_AIN1 ((uint8_t)0x01)
/* Passthrough B select - NONE */
#define CS43L22_PSELB_NONE ((uint8_t)0x00)
/* Passthrough B select - AIN2 */
#define CS43L22_PSELB_AIN2 ((uint8_t)0x02)
/* Analog zero cross / soft ramp */
#define CS43L22_REG_AZCSR 0x0a
/* Analog zero cross / soft ramp - Channel B soft ramp - Enabled */
#define CS43L22_AZCSR_SRB_ON ((uint8_t)0x08)
/* Analog zero cross / soft ramp - Channel B soft ramp - Disabled */
#define CS43L22_AZCSR_SRB_OFF ((uint8_t)0x00)
/* Analog zero cross / soft ramp - Channel A soft ramp - Enabled */
#define CS43L22_AZCSR_SRA_ON ((uint8_t)0x04)
/* Analog zero cross / soft ramp - Channel A soft ramp - Disabled */
#define CS43L22_AZCSR_SRA_OFF ((uint8_t)0x00)
/* Analog zero cross / soft ramp - Channel B zero cross - Disabled */
#define CS43L22_AZCSR_ZCB_OFF ((uint8_t)0x00)
/* Analog zero cross / soft ramp - Channel B zero cross - Enabled */
#define CS43L22_AZCSR_ZCB_ON ((uint8_t)0x02)
/* Analog zero cross / soft ramp - Channel A zero cross - Enabled */
#define CS43L22_AZCSR_ZCA_ON ((uint8_t)0x01)
/* Analog zero cross / soft ramp - Channel A zero cross - Disabled */
#define CS43L22_AZCSR_ZCA_OFF ((uint8_t)0x00)
/* Passthrough gang control */
#define CS43L22_REG_PGC 0x0c
/* Passthrough gang control - Enabled */
#define CS43L22_PGC_ON ((uint8_t)0x80)
/* Passthrough gang control - Disabled */
#define CS43L22_PGC_OFF ((uint8_t)0x00)
/* Playback control 1 */
#define CS43L22_REG_PB_CTL1 0x0d
/* Playback control 1 - Headphone analog gain - Mask */
#define CS43L22_PB1_HGAIN_MASK ((uint8_t)0xe0)
/* Playback control 1 - Ganged volume control - Disabled */
#define CS43L22_PB1_SAMEVOLUME_OFF ((uint8_t)0x00)
/* Playback control 1 - Ganged volume control - Enabled */
#define CS43L22_PB1_SAMEVOLUME_ON ((uint8_t)0x10)
/* Playback control 1 - Invert channel B polarity - Enabled */
#define CS43L22_PB1_INVB_ON ((uint8_t)0x08)
/* Playback control 1 - Invert channel B polarity - Disabled */
#define CS43L22_PB1_INVB_OFF ((uint8_t)0x00)
/* Playback control 1 - Invert channel A polarity - Enabled */
#define CS43L22_PB1_INVA_ON ((uint8_t)0x04)
/* Playback control 1 - Invert channel A polarity - Disabled */
#define CS43L22_PB1_INVA_OFF ((uint8_t)0x00)
/* Playback control 1 - Channel B muted - Disabled */
#define CS43L22_PB1_MUTEB_OFF ((uint8_t)0x00)
/* Playback control 1 - Channel B muted - Enabled */
#define CS43L22_PB1_MUTEB_ON ((uint8_t)0x02)
/* Playback control 1 - Channel A muted - Enabled */
#define CS43L22_PB1_MUTEA_ON ((uint8_t)0x01)
/* Playback control 1 - Channel A muted - Disabled */
#define CS43L22_PB1_MUTEA_OFF ((uint8_t)0x00)
/* Miscellaneous controls */
#define CS43L22_REG_MISC_CTL 0x0e
/* Miscellaneous controls - Passthrough analog B - Enabled */
#define CS43L22_MISC_PTHRUB_ON ((uint8_t)0x80)
/* Miscellaneous controls - Passthrough analog B - Disabled */
#define CS43L22_MISC_PTHRUB_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Passthrough analog A - Enabled */
#define CS43L22_MISC_PTHRUA_ON ((uint8_t)0x40)
/* Miscellaneous controls - Passthrough analog A - Disabled */
#define CS43L22_MISC_PTHRUA_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Passthrough mute B - Enabled */
#define CS43L22_MISC_PTMUTEB_ON ((uint8_t)0x20)
/* Miscellaneous controls - Passthrough mute B - Disabled */
#define CS43L22_MISC_PTMUTEB_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Passthrough mute A - Disabled */
#define CS43L22_MISC_PTMUTEA_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Passthrough mute A - Enabled */
#define CS43L22_MISC_PTMUTEA_ON ((uint8_t)0x10)
/* Miscellaneous controls - Freeze registers - Enabled */
#define CS43L22_MISC_FREEZE_ON ((uint8_t)0x08)
/* Miscellaneous controls - Freeze registers - Disabled */
#define CS43L22_MISC_FREEZE_OFF ((uint8_t)0x00)
/* Miscellaneous controls - De-emphasis filter - Enabled */
#define CS43L22_MISC_DEEMPHASIS_ON ((uint8_t)0x04)
/* Miscellaneous controls - De-emphasis filter - Disabled */
#define CS43L22_MISC_DEEMPHASIS_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Digital soft ramp - Disabled */
#define CS43L22_MISC_DSR_OFF ((uint8_t)0x00)
/* Miscellaneous controls - Digital soft ramp - Enabled */
#define CS43L22_MISC_DSR_ON ((uint8_t)0x02)
/* Miscellaneous controls - Digital zero cross - Enabled */
#define CS43L22_MISC_DZC_ON ((uint8_t)0x01)
/* Miscellaneous controls - Digital zero cross - Disabled */
#define CS43L22_MISC_DZC_OFF ((uint8_t)0x00)
/* Playback control 2 */
#define CS43L22_REG_PB_CTL2 0x0f
/* Playback control 2 - Headphone B mute - Enabled */
#define CS43L22_PB2_HPB_MUTE_ON ((uint8_t)0x80)
/* Playback control 2 - Headphone B mute - Disabled */
#define CS43L22_PB2_HPB_MUTE_OFF ((uint8_t)0x00)
/* Playback control 2 - Headphone A mute - Enabled */
#define CS43L22_PB2_HPA_MUTE_ON ((uint8_t)0x40)
/* Playback control 2 - Headphone A mute - Disabled */
#define CS43L22_PB2_HPA_MUTE_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker B mute - Enabled */
#define CS43L22_PB2_SPKB_MUTE_ON ((uint8_t)0x20)
/* Playback control 2 - Speaker B mute - Disabled */
#define CS43L22_PB2_SPKB_MUTE_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker A mute - Disabled */
#define CS43L22_PB2_SPKA_MUTE_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker A mute - Enabled */
#define CS43L22_PB2_SPKA_MUTE_ON ((uint8_t)0x10)
/* Playback control 2 - Ganged speaker volume settings - Enabled */
#define CS43L22_PB2_SPK_GANG_ON ((uint8_t)0x08)
/* Playback control 2 - Ganged speaker volume settings - Disabled */
#define CS43L22_PB2_SPK_GANG_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker channel swap - Enabled */
#define CS43L22_PB2_SPK_SWAP_ON ((uint8_t)0x04)
/* Playback control 2 - Speaker channel swap - Disabled */
#define CS43L22_PB2_SPK_SWAP_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker mono mode - Disabled */
#define CS43L22_PB2_SPK_MONO_OFF ((uint8_t)0x00)
/* Playback control 2 - Speaker mono mode - Enabled */
#define CS43L22_PB2_SPK_MONO_ON ((uint8_t)0x02)
/* Playback control 2 - Speaker mute 50/50 control - Enabled */
#define CS43L22_PB2_SPK_M50_ON ((uint8_t)0x01)
/* Playback control 2 - Speaker mute 50/50 control - Disabled */
#define CS43L22_PB2_SPK_M50_OFF ((uint8_t)0x00)
/* Passthrough volume (channel A) */
#define CS43L22_REG_PASS_A_VOL 0x14
/* Passthrough volume (channel B) */
#define CS43L22_REG_PASS_B_VOL 0x15
/* PCM channel A control */
#define CS43L22_REG_PCM_A 0x1a
/* PCM channel A control - Mute channel - Enabled */
#define CS43L22_PCM_A_MUTE_ON ((uint8_t)0x80)
/* PCM channel A control - Mute channel - Disabled */
#define CS43L22_PCM_A_MUTE_OFF ((uint8_t)0x00)
/* PCM channel A control - Channel volume - Mask */
#define CS43L22_PCM_A_VOLUME_MASK ((uint8_t)0x7f)
/* PCM channel B control */
#define CS43L22_REG_PCM_B 0x1b
/* PCM channel B control - Mute channel - Enabled */
#define CS43L22_PCM_B_MUTE_ON ((uint8_t)0x80)
/* PCM channel B control - Mute channel - Disabled */
#define CS43L22_PCM_B_MUTE_OFF ((uint8_t)0x00)
/* PCM channel B control - Channel volume - Mask */
#define CS43L22_PCM_B_VOLUME_MASK ((uint8_t)0x7f)
/* Beep control 1 */
#define CS43L22_REG_BEEP_CTL1 0x1c
/* Beep control 1 - Frequency - Mask */
#define CS43L22_BEEP_FREQ_MASK ((uint8_t)0xf0)
/* Beep control 1 - Duration - Mask */
#define CS43L22_BEEP_ONTIME_MASK ((uint8_t)0x0f)
/* Beep control 2 */
#define CS43L22_REG_BEEP_CTL2 0x1d
/* Beep control 2 - Off time - Mask */
#define CS43L22_BEEP_OFFTIME_MASK ((uint8_t)0xf0)
/* Beep control 2 - Volume - Mask */
#define CS43L22_BEEP_VOL_MASK ((uint8_t)0x0f)
/* Beep & tone configuration */
#define CS43L22_REG_BEEP_TONE_CFG 0x1e
/* Beep & tone configuration - Beep configuration - Multiple */
#define CS43L22_B3_BEEP_CFG_MULTI ((uint8_t)0x80)
/* Beep & tone configuration - Beep configuration - Single */
#define CS43L22_B3_BEEP_CFG_SINGLE ((uint8_t)0x40)
/* Beep & tone configuration - Beep configuration - Off */
#define CS43L22_B3_BEEP_CFG_OFF ((uint8_t)0x00)
/* Beep & tone configuration - Beep configuration - Continuous */
#define CS43L22_B3_BEEP_CFG_CONT ((uint8_t)0xc0)
/* Beep & tone configuration - Beep mix disable - OFF */
#define CS43L22_B3_BEEP_NOMIX_OFF ((uint8_t)0x20)
/* Beep & tone configuration - Beep mix disable - ON */
#define CS43L22_B3_BEEP_NOMIX_ON ((uint8_t)0x00)
/* Beep & tone configuration - Treble corner frequency - 7KHZ */
#define CS43L22_B3_TREBLE_CF_7KHZ ((uint8_t)0x08)
/* Beep & tone configuration - Treble corner frequency - 5KHZ */
#define CS43L22_B3_TREBLE_CF_5KHZ ((uint8_t)0x00)
/* Beep & tone configuration - Treble corner frequency - 15KHZ */
#define CS43L22_B3_TREBLE_CF_15KHZ ((uint8_t)0x18)
/* Beep & tone configuration - Treble corner frequency - 10KHZ */
#define CS43L22_B3_TREBLE_CF_10KHZ ((uint8_t)0x10)
/* Beep & tone configuration - Bass corner frequency - 250HZ */
#define CS43L22_B3_BASS_CF_250HZ ((uint8_t)0x06)
/* Beep & tone configuration - Bass corner frequency - 200HZ */
#define CS43L22_B3_BASS_CF_200HZ ((uint8_t)0x04)
/* Beep & tone configuration - Bass corner frequency - 50HZ */
#define CS43L22_B3_BASS_CF_50HZ ((uint8_t)0x00)
/* Beep & tone configuration - Bass corner frequency - 100HZ */
#define CS43L22_B3_BASS_CF_100HZ ((uint8_t)0x02)
/* Beep & tone configuration - Tone control - Enabled */
#define CS43L22_B3_TONECTL_ON ((uint8_t)0x01)
/* Beep & tone configuration - Tone control - Disabled */
#define CS43L22_B3_TONECTL_OFF ((uint8_t)0x00)
/* Tone control */
#define CS43L22_REG_TONE_CTL 0x1f
/* Tone control - Treble gain - Mask */
#define CS43L22_TCTL_TREBLE_MASK ((uint8_t)0xf0)
/* Tone control - Bass gain - Mask */
#define CS43L22_TCTL_BASS_MASK ((uint8_t)0x0f)
/* Master volume control (channel A) */
#define CS43L22_REG_MASTER_VOLUME_A 0x20
/* Master volume control (channel B) */
#define CS43L22_REG_MASTER_VOLUME_B 0x21
/* Headphone volume control (channel A) */
#define CS43L22_REG_HP_VOLUME_A 0x22
/* Headphone volume control (channel B) */
#define CS43L22_REG_HP_VOLUME_B 0x23
/* Speaker volume control (channel A) */
#define CS43L22_REG_SPK_VOLUME_A 0x24
/* Speaker volume control (channel B) */
#define CS43L22_REG_SPK_VOLUME_B 0x25
/* PCM channel swap */
#define CS43L22_REG_PCM_SWAP 0x26
/* PCM channel swap - Channel A - (Left + Right) / 2 */
#define CS43L22_PCS_A_MIX ((uint8_t)0x40)
/* PCM channel swap - Channel A - Left */
#define CS43L22_PCS_A_LEFT ((uint8_t)0x00)
/* PCM channel swap - Channel A - Right */
#define CS43L22_PCS_A_RIGHT ((uint8_t)0xc0)
/* PCM channel swap - Channel B - Right */
#define CS43L22_PCS_B_RIGHT ((uint8_t)0x00)
/* PCM channel swap - Channel B - (Left + Right) / 2 */
#define CS43L22_PCS_B_MIX ((uint8_t)0x10)
/* PCM channel swap - Channel B - Left */
#define CS43L22_PCS_B_LEFT ((uint8_t)0x30)
/* Limiter control 1 */
#define CS43L22_REG_LIM_CTL1 0x27
/* Limiter control 1 - Maximum threshold - Mask */
#define CS43L22_LIM1_MAX_MASK ((uint8_t)0xe0)
/* Limiter control 1 - Cushion threshold - Mask */
#define CS43L22_LIM1_CUSHION_MASK ((uint8_t)0x1c)
/* Limiter control 1 - Soft ramp - Use digital soft ramp */
#define CS43L22_LIM1_SRD_OFF ((uint8_t)0x00)
/* Limiter control 1 - Soft ramp - Ignore digital soft ramp */
#define CS43L22_LIM1_SRD_ON ((uint8_t)0x02)
/* Limiter control 1 - Zero cross - Ignore digital zero cross */
#define CS43L22_LIM1_ZCD_ON ((uint8_t)0x01)
/* Limiter control 1 - Zero cross - Use digital zero cross */
#define CS43L22_LIM1_ZCD_OFF ((uint8_t)0x00)
/* Limiter control 2 */
#define CS43L22_REG_LIM_CTL2 0x28
/* Limiter control 2 - Peak detect and limiter - Enabled */
#define CS43L22_LIM2_ON ((uint8_t)0x80)
/* Limiter control 2 - Peak detect and limiter - Disabled */
#define CS43L22_LIM2_OFF ((uint8_t)0x00)
/* Limiter control 2 - Limit both channels - Enabled */
#define CS43L22_LIM2_LAC_ON ((uint8_t)0x40)
/* Limiter control 2 - Limit both channels - Disabled */
#define CS43L22_LIM2_LAC_OFF ((uint8_t)0x00)
/* Limiter control 2 - Release rate - Mask */
#define CS43L22_LIM2_RRATE_MASK ((uint8_t)0x3f)
/* Limiter control 3 */
#define CS43L22_REG_LIM_CTL3 0x29
/* Limiter control 3 - Attack rate - Mask */
#define CS43L22_LIM3_ARATE_MASK ((uint8_t)0x3f)
/* Status (RO) */
#define CS43L22_REG_STATUS 0x2e
/* Status (RO) - Serial port clock error */
#define CS43L22_STATUS_SERIAL_ERROR ((uint8_t)0x40)
/* Status (RO) - DSP A overflow */
#define CS43L22_STATUS_DSP_A_OVERFLOW ((uint8_t)0x20)
/* Status (RO) - DSP B overflow */
#define CS43L22_STATUS_DSP_B_OVERFLOW ((uint8_t)0x10)
/* Status (RO) - PCM A overflow */
#define CS43L22_STATUS_PCM_A_OVERFLOW ((uint8_t)0x08)
/* Status (RO) - PCM B overflow */
#define CS43L22_STATUS_PCM_B_OVERFLOW ((uint8_t)0x04)
/* Battery compensation */
#define CS43L22_REG_BATTERY_COMPENSATION 0x2f
/* Battery compensation - Enabled */
#define CS43L22_BC_ON ((uint8_t)0x80)
/* Battery compensation - Disabled */
#define CS43L22_BC_OFF ((uint8_t)0x00)
/* Battery compensation - VP voltage level monitor - Enabled */
#define CS43L22_BC_VPM_ON ((uint8_t)0x40)
/* Battery compensation - VP voltage level monitor - Disabled */
#define CS43L22_BC_VPM_OFF ((uint8_t)0x00)
/* Battery compensation - VP reference - Mask */
#define CS43L22_BC_VPREF_MASK ((uint8_t)0x0f)
/* Battery level (RO) */
#define CS43L22_REG_BATTERY_LEVEL 0x30
/* Speaker status (RO) */
#define CS43L22_REG_SPKR_STATUS 0x31
/* Speaker status (RO) - Channel A overload detected */
#define CS43L22_SPKS_OVERLOAD_A ((uint8_t)0x20)
/* Speaker status (RO) - Channel B overload detected */
#define CS43L22_SPKS_OVERLOAD_B ((uint8_t)0x10)
/* Speaker status (RO) - Speaker/headphones pin status */
#define CS43L22_SPKS_SPKHP_SWITCH ((uint8_t)0x08)
/* Charge pump frequency */
#define CS43L22_REG_CPFREQ 0x34
/* Charge pump frequency - Mask */
#define CS43L22_CPFREQ_MASK ((uint8_t)0xf0)
#endif //__H_CS43L22

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#ifndef __H_PINS_CS43L22
#define __H_PINS_CS43L22
// Alternate function used for I2S to the CS43L22
#define I2S_OUT_FUNCTION 6
// CS43L22 reset pin and delay
#define I2S_ORESET_PORT GPIOD
#define I2S_ORESET_PAD 4
#define I2S_ORESET_DELAY 10
// CS43L22 SCL pin
#define I2C_OSCL_PORT GPIOB
#define I2C_OSCL_PAD 6
// CS43L22 SDA pin
#define I2C_OSDA_PORT GPIOB
#define I2C_OSDA_PAD 9
// CS43L22 WS pin
#define I2S_OWS_PORT GPIOA
#define I2S_OWS_PAD 4
// CS43L22 MCK pin
#define I2S_OMCK_PORT GPIOC
#define I2S_OMCK_PAD 7
// CS43L22 SCK pin
#define I2S_OSCK_PORT GPIOC
#define I2S_OSCK_PAD 10
// CS43L22 SD pin
#define I2S_OSD_PORT GPIOC
#define I2S_OSD_PAD 12
// Output control I2C parameters
#define I2S_OI2C_DRIVER I2CD1
#define I2S_OI2C_SPEED 400000
#define I2S_OI2C_ADDRESS 0x4a
#define I2S_OI2C_TIMEOUT 1000
// Base address of the SPI port
#define I2S_SPI_BASE SPI3_BASE
#endif //__H_PINS_CS43L22

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C TRUE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Block size for MMC transfers.
*/
#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
#define MMC_SECTOR_SIZE 512
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/**
* @brief Number of positive insertion queries before generating the
* insertion event.
*/
#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
#define MMC_POLLING_INTERVAL 10
#endif
/**
* @brief Interval, in milliseconds, between insertion queries.
*/
#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
#define MMC_POLLING_DELAY 10
#endif
/**
* @brief Uses the SPI polled API for small data transfers.
* @details Polled transfers usually improve performance because it
* saves two context switches and interrupt servicing. Note
* that this option has no effect on large transfers which
* are always performed using DMAs/IRQs.
*/
#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
#define MMC_USE_SPI_POLLING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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#ifndef __H_STM32F4_I2S
#define __H_STM32F4_I2S
/* I2S configuration */
#define STM32F4_I2S_OFFS_CFG 0x0000001c
/* I2S configuration - SPI mode */
#define STM32F4_I2S_CFG_MODE_SPI ((uint16_t)0x0000)
/* I2S configuration - I2S mode */
#define STM32F4_I2S_CFG_MODE_I2S ((uint16_t)0x0800)
/* I2S configuration - Peripheral enabled */
#define STM32F4_I2S_CFG_ENABLED ((uint16_t)0x0400)
/* I2S configuration - Peripheral disabled */
#define STM32F4_I2S_CFG_DISABLED ((uint16_t)0x0000)
/* I2S configuration - I2S configuration mode - Master/transmit */
#define STM32F4_I2S_CFG_CFG_MS_TX ((uint16_t)0x0200)
/* I2S configuration - I2S configuration mode - Slave/transmit */
#define STM32F4_I2S_CFG_CFG_SL_TX ((uint16_t)0x0000)
/* I2S configuration - I2S configuration mode - Slave/receive */
#define STM32F4_I2S_CFG_CFG_SL_RX ((uint16_t)0x0100)
/* I2S configuration - I2S configuration mode - Master/receive */
#define STM32F4_I2S_CFG_CFG_MS_RX ((uint16_t)0x0300)
/* I2S configuration - PCM frame sync - Long frame */
#define STM32F4_I2S_CFG_PCMSYNC_LONG ((uint16_t)0x0080)
/* I2S configuration - PCM frame sync - Short frame */
#define STM32F4_I2S_CFG_PCMSYNC_SHORT ((uint16_t)0x0000)
/* I2S configuration - I2S standard - Right justified */
#define STM32F4_I2S_CFG_STD_LSB ((uint16_t)0x0020)
/* I2S configuration - I2S standard - I2S Philips standard */
#define STM32F4_I2S_CFG_STD_I2S ((uint16_t)0x0000)
/* I2S configuration - I2S standard - Left justified */
#define STM32F4_I2S_CFG_STD_MSB ((uint16_t)0x0010)
/* I2S configuration - I2S standard - PCM standard */
#define STM32F4_I2S_CFG_STD_PCM ((uint16_t)0x0030)
/* I2S configuration - Reverse clock polarity - ON */
#define STM32F4_I2S_CFG_RCPOL_ON ((uint16_t)0x0008)
/* I2S configuration - Reverse clock polarity - OFF */
#define STM32F4_I2S_CFG_RCPOL_OFF ((uint16_t)0x0000)
/* I2S configuration - Data length - 32-bit */
#define STM32F4_I2S_CFG_DLEN_32 ((uint16_t)0x0004)
/* I2S configuration - Data length - 16-bit */
#define STM32F4_I2S_CFG_DLEN_16 ((uint16_t)0x0000)
/* I2S configuration - Data length - 24-bit */
#define STM32F4_I2S_CFG_DLEN_24 ((uint16_t)0x0002)
/* I2S configuration - Channel length - 32-bit */
#define STM32F4_I2S_CFG_CLEN_32 ((uint16_t)0x0001)
/* I2S configuration - Channel length - 16-bit */
#define STM32F4_I2S_CFG_CLEN_16 ((uint16_t)0x0000)
/* I2S prescaler */
#define STM32F4_I2S_OFFS_PR 0x00000020
/* I2S prescaler - Master clock output - ON */
#define STM32F4_I2S_PR_MCLK_ON ((uint16_t)0x0200)
/* I2S prescaler - Master clock output - OFF */
#define STM32F4_I2S_PR_MCLK_OFF ((uint16_t)0x0000)
/* I2S prescaler - Odd factor - Divider is I2SDIV * 2 */
#define STM32F4_I2S_PR_EVEN ((uint16_t)0x0000)
/* I2S prescaler - Odd factor - Divider is 1 + I2SDIV * 2 */
#define STM32F4_I2S_PR_ODD ((uint16_t)0x0100)
/* I2S prescaler - Divider - Mask */
#define STM32F4_I2S_PR_DIV_MASK ((uint16_t)0x00ff)
#endif //__H_STM32F4_I2S

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#include "ch.h"
#include "hal.h"
#include "chprintf.h"
#include "serial_output.h"
#include "sound.h"
// This is called when the board boots up with the user button pressed. The
// idea is to enter this mode if the wrong SPI device has been used and flashing
// is no longer possible.
__attribute__ ((noreturn))
static void lockdown( void )
{
palSetPad( GPIOD , GPIOD_LED3 );
while (TRUE) {
// EMPTY
}
}
static int increment;
static int curPos;
static const s16 sinTable[16384] = {
#include "sin_table.h"
};
void debug(void)
{
chprintf( (void*)&SD2 , "I2S:\r\n" );
chprintf( (void*)&SD2 , " CR2 %x\r\n" , SPI3->CR2 );
chprintf( (void*)&SD2 , " SR %x\r\n" , SPI3->SR );
chprintf( (void*)&SD2 , " CFG %x\r\n" , SPI3->I2SCFGR );
chprintf( (void*)&SD2 , " PR %x\r\n" , SPI3->I2SPR );
chprintf( (void*)&SD2 , "DMA:\r\n" );
chprintf( (void*)&SD2 , " CR %x\r\n" ,
SPID3.dmatx->stream->CR );
chprintf( (void*)&SD2 , " NDT %x\r\n" ,
SPID3.dmatx->stream->NDTR );
chprintf( (void*)&SD2 , " PAR %x\r\n" ,
SPID3.dmatx->stream->PAR );
chprintf( (void*)&SD2 , " M0A %x\r\n" ,
SPID3.dmatx->stream->M0AR );
chprintf( (void*)&SD2 , " M1A %x\r\n" ,
SPID3.dmatx->stream->M1AR );
chprintf( (void*)&SD2 , " FCR %x\r\n" ,
SPID3.dmatx->stream->FCR );
chprintf( (void*)&SD2 , "curPos: %d\r\n" , curPos );
}
__attribute__ ((noreturn))
int main( void )
{
halInit();
chSysInit();
if ( palReadPad( GPIOA , GPIOA_BUTTON ) ) {
lockdown( );
}
soInit( );
chprintf( (void*)&SD2 , "Sound card initialisation\r\n" );
sndInit( 11025 );
chprintf( (void*)&SD2 ,
"Sound card initialisation complete\r\n" );
increment = 654; // 16384 * 440 / 11025
curPos = 0;
debug( );
#ifdef USE_DMA_FOR_SEXY_BEEPS
int i = 0;
while ( 1 ) {
s16 * buffer = sndGetBuffer( );
if ( buffer == NULL ) {
i ++;
if ( i == 2000000 ) {
i = 0;
palTogglePad( GPIOD , GPIOD_LED4 );
debug( );
}
continue;
}
palTogglePad( GPIOD , GPIOD_LED3 );
int z;
for ( z = 0 ; z < SND_BUFSIZE / 2 ; z ++ ) {
buffer[ z * 2 ] = buffer[ z * 2 + 1 ]
= sinTable[ curPos ];
curPos = ( curPos + increment / 2 ) % 16384;
}
}
#else // USE_DMA_FOR_SEXY_BEEPS
int i = 0;
while ( 1 ) {
u16 sr = SPI3->SR;
if ( ( sr & 0x2 ) == 0 ) {
continue;
}
SPI3->DR = sinTable[ curPos ];
if ( ( sr & 0x4 ) == 0 ) {
curPos = ( curPos + increment ) % 16384;
}
i ++;
if ( i == 22100 ) {
i = 0;
palTogglePad( GPIOD , GPIOD_LED4 );
debug( );
}
}
#endif // USE_DMA_FOR_SEXY_BEEPS
}

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define HSE_VALUE 8000000
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_VOS STM32_VOS_HIGH
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0

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#include "ch.h"
#include "hal.h"
#include "serial_output.h"
void soInit( void )
{
sdStart( &SERIALOUT_DRIVER , NULL );
palSetPadMode( SERIALOUT_TX_PORT , SERIALOUT_TX_PAD ,
PAL_MODE_ALTERNATE( SERIALOUT_AF ) );
palSetPadMode( SERIALOUT_RX_PORT , SERIALOUT_RX_PAD ,
PAL_MODE_ALTERNATE( SERIALOUT_AF ) );
}

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#ifndef __H_SERIALOUT
#define __H_SERIALOUT
#define SERIALOUT_DRIVER SD2
#define SERIALOUT_TX_PORT GPIOA
#define SERIALOUT_TX_PAD 2
#define SERIALOUT_RX_PORT GPIOA
#define SERIALOUT_RX_PAD 3
#define SERIALOUT_AF 7
void soInit( void );
#endif // __H_SERIALOUT

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#include "ch.h"
#include "hal.h"
#include "chprintf.h"
#include "stm32f4xx.h"
#include "sound.h"
#include "i2s_bits.h"
#include "cs43l22_pins.h"
#include "cs43l22_commands.h"
/* I2C driver configuration */
static const I2CConfig _i2s_i2c_config = {
OPMODE_I2C , // Operation mode
I2S_OI2C_SPEED , // Clock frequency
FAST_DUTY_CYCLE_2 // Duty cycle
};
/* Initialise one of the I2C pads */
#define _i2s_init_i2c_pad(port,pad) \
palSetPadMode( port , pad , \
PAL_STM32_OTYPE_OPENDRAIN | PAL_STM32_OSPEED_MID2 \
| PAL_MODE_ALTERNATE(4) )
/* Initialise an I2S pad */
#define _i2s_init_i2s_pad(port,pad) \
palSetPadMode( port , pad , \
PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_MID2 \
| PAL_STM32_ALTERNATE( I2S_OUT_FUNCTION ) )
/* Currently playing? */
static int _snd_playing;
/* May write next buffer? */
static int _snd_next_ok;
/* Last initialised buffer */
static int _snd_init_buffer;
/* Buffers */
static s16 _snd_buffers[ 2 * SND_BUFSIZE ];
/* Compute a buffer's address */
#define _snd_buffer_address(idx) \
(& _snd_buffers[ (idx) * SND_BUFSIZE ] )
#ifdef USE_DMA_FOR_SEXY_BEEPS
/* SPI transfer callback, used when buffers need to be rotated */
static void _cs43l22_spi_callback( SPIDriver * driver , u32 flags )
{
if ( driver != &SPID3 || !( flags & STM32_DMA_ISR_TCIF ) ) {
return;
}
extern u32 isrFlags;
isrFlags = flags;
_snd_next_ok = TRUE;
}
#endif // USE_DMA_FOR_SEXY_BEEPS
/*
* Initialise GPIO ports to handle:
* - the CS43L22's I2C channel,
* - the CS43L22's I2S channel.
*/
static void _i2s_init_gpio( void )
{
// Reset pin
palSetPadMode( I2S_ORESET_PORT , I2S_ORESET_PAD ,
PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_MID2 );
// SDL/SDA pins
_i2s_init_i2c_pad( I2C_OSCL_PORT , I2C_OSCL_PAD );
_i2s_init_i2c_pad( I2C_OSDA_PORT , I2C_OSDA_PAD );
// I2S WS/MCK/SCK/SD pins
_i2s_init_i2s_pad( I2S_OWS_PORT , I2S_OWS_PAD );
_i2s_init_i2s_pad( I2S_OMCK_PORT , I2S_OMCK_PAD );
_i2s_init_i2s_pad( I2S_OSCK_PORT , I2S_OSCK_PAD );
_i2s_init_i2s_pad( I2S_OSD_PORT , I2S_OSD_PAD );
}
/* Reset the CS43L22 */
static void _i2s_reset_output( void )
{
palClearPad( I2S_ORESET_PORT , I2S_ORESET_PAD );
chThdSleep( I2S_ORESET_DELAY );
palSetPad( I2S_ORESET_PORT , I2S_ORESET_PAD );
chThdSleep( I2S_ORESET_DELAY );
}
/* Send a command to the CS43L22 through I2C */
static msg_t _cs43l22_set( u8 reg , u8 value )
{
u8 txBuffer[ 2 ];
txBuffer[0] = reg;
txBuffer[1] = value;
msg_t rv = i2cMasterTransmitTimeout(
& I2S_OI2C_DRIVER , I2S_OI2C_ADDRESS ,
txBuffer , 2 ,
NULL , 0 ,
I2S_OI2C_TIMEOUT );
if ( rv ) {
chprintf( (void*)&SD2 ,
"I2C 0x%0.2x <- 0x%0.2x ERROR %d\r\n" ,
reg , value , rv );
chprintf( (void*)&SD2 ,
" status = 0x%x\r\n" ,
i2cGetErrors( & I2S_OI2C_DRIVER ) );
} else {
chprintf( (void*)&SD2 ,
"I2C 0x%0.2x <- 0x%0.2x OK\r\n" ,
reg , value );
}
return rv;
}
/* Get a register from the CS43L22 through I2C */
static u8 _cs43l22_get( u8 reg )
{
u8 data;
msg_t rv = i2cMasterTransmitTimeout(
& I2S_OI2C_DRIVER , I2S_OI2C_ADDRESS ,
&reg , 1 ,
&data , 1 ,
I2S_OI2C_TIMEOUT );
if ( rv ) {
chprintf( (void*)&SD2 ,
"I2C 0x%0.2x >- ??? ERROR %d\r\n" ,
reg , rv );
chprintf( (void*)&SD2 ,
" status = 0x%x\r\n" ,
i2cGetErrors( & I2S_OI2C_DRIVER ) );
}
return data;
}
/* Initialise the CS43L22 through its I2C interface */
static void _cs43l22_init( void )
{
i2cStart( &( I2S_OI2C_DRIVER ) , &_i2s_i2c_config );
// Make sure the device is powered down
_cs43l22_set( CS43L22_REG_PWR_CTL1 , CS43L22_PWR1_DOWN );
// Activate headphone channels
_cs43l22_set( CS43L22_REG_PWR_CTL2 ,
CS43L22_PWR2_SPKA_OFF | CS43L22_PWR2_SPKB_OFF
| CS43L22_PWR2_HDA_ON | CS43L22_PWR2_HDB_ON );
// Set serial clock
_cs43l22_set( CS43L22_REG_CLOCK_CTL , CS43L22_CLK_AUTO_ON
| CS43L22_CLK_MCDIV_ON );
// Set input data format
_cs43l22_set( CS43L22_REG_INT_CTL1 , CS43L22_IC1_SLAVE
| CS43L22_IC1_SCPOL_OFF | CS43L22_IC1_DSP_OFF
| CS43L22_IC1_DIF_I2S | CS43L22_IC1_AWL_32 );
// Fire it up
_cs43l22_set( CS43L22_REG_PWR_CTL1 , CS43L22_PWR1_UP );
// Analog soft ramp/zero cross disabled
_cs43l22_set( CS43L22_REG_AZCSR ,
CS43L22_AZCSR_SRB_OFF | CS43L22_AZCSR_SRA_OFF
| CS43L22_AZCSR_ZCB_OFF | CS43L22_AZCSR_ZCA_OFF );
// Digital soft ramp disabled
_cs43l22_set( CS43L22_REG_MISC_CTL , CS43L22_MISC_DEEMPHASIS_ON );
// Limiter: no soft ramp/zero cross, no attack level
_cs43l22_set( CS43L22_REG_LIM_CTL1 , CS43L22_LIM1_SRD_OFF
| CS43L22_LIM1_ZCD_OFF );
// Initial volume and tone controls
_cs43l22_set( CS43L22_REG_TONE_CTL , 0xf );
_cs43l22_set( CS43L22_REG_PCM_A , 0x00 );
_cs43l22_set( CS43L22_REG_PCM_B , 0x00 );
sndOutputVolume( 200 );
}
/* Initialise the I2S interface to the CS43L22 */
static void _cs43l22_init_i2s( u32 frequency )
{
rccEnableSPI3(FALSE);
u32 plln = ( RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN ) >> 6;
u32 pllr = ( RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR ) >> 28;
u32 pllm = (u32)( RCC->PLLCFGR & RCC_PLLCFGR_PLLM );
u32 clock = (u32)( ( ( HSE_VALUE / pllm ) * plln ) / pllr );
chprintf( (void*)&SD2 , "PLL REG=0x%.x N=%d R=%d M=%d CLK = %d\r\n" ,
RCC->PLLI2SCFGR , plln , pllr , pllm , clock );
u16 frq = (u16)(( ( ( clock / 256 ) * 10 ) / frequency ) + 5 ) / 10;
chprintf( (void*)&SD2 , "frq base = 0x%x\r\n" , frq );
if ( ( frq & 1 ) == 0 ) {
frq = frq >> 1;
} else {
frq = STM32F4_I2S_PR_ODD | ( frq >> 1 );
}
chprintf( (void*)&SD2 , "frq = 0x%x\r\n" , frq );
*((u32*)(SPI3_BASE + STM32F4_I2S_OFFS_CFG)) =
STM32F4_I2S_CFG_MODE_I2S
| STM32F4_I2S_CFG_STD_I2S
| STM32F4_I2S_CFG_CFG_MS_TX
| STM32F4_I2S_CFG_RCPOL_OFF
| STM32F4_I2S_CFG_DLEN_16
| STM32F4_I2S_CFG_CLEN_16;
*((u32*)(SPI3_BASE + STM32F4_I2S_OFFS_PR)) = frq
| STM32F4_I2S_PR_MCLK_ON;
*((u32*)(SPI3_BASE + STM32F4_I2S_OFFS_CFG)) |= STM32F4_I2S_CFG_ENABLED;
}
#ifdef USE_DMA_FOR_SEXY_BEEPS
static void _cs43l22_init_dma( void )
{
dmaStreamAllocate( SPID3.dmatx , 1 ,
(stm32_dmaisr_t) _cs43l22_spi_callback ,
&SPID3 );
SPID3.txdmamode |= ( STM32_DMA_CR_PSIZE_HWORD | 0x30000
| STM32_DMA_CR_MINC | STM32_DMA_CR_MSIZE_HWORD
| STM32_DMA_CR_DBM | STM32_DMA_CR_TCIE );
dmaStreamSetMode( SPID3.dmatx , SPID3.txdmamode );
dmaStreamSetFIFO( SPID3.dmatx , STM32_DMA_FCR_DMDIS
| STM32_DMA_FCR_FTH_HALF );
dmaStreamSetPeripheral( SPID3.dmatx , &( SPID3.spi->DR ) );
SPID3.spi->CR2 |= SPI_CR2_TXDMAEN;
}
#endif // USE_DMA_FOR_SEXY_BEEPS
void sndInit( u32 frequency )
{
_i2s_init_gpio( );
_i2s_reset_output( );
_cs43l22_init( );
_cs43l22_init_i2s( frequency );
#ifdef USE_DMA_FOR_SEXY_BEEPS
_cs43l22_init_dma( );
#endif // USE_DMA_FOR_SEXY_BEEPS
_snd_next_ok = TRUE;
}
void sndOutputVolume( u8 volume )
{
if ( volume > 0xe6 ) {
volume -= 0xe7;
} else {
volume += 0x19;
}
_cs43l22_set( CS43L22_REG_MASTER_VOLUME_A , volume );
_cs43l22_set( CS43L22_REG_MASTER_VOLUME_B , volume );
}
s16 * sndGetBuffer( void )
{
if ( ! _snd_next_ok ) {
return NULL;
}
int next_write;
if ( _snd_playing ) {
next_write = ( SPID3.dmatx->stream->CR & 0x80000 )
? 0 : 1;
_snd_next_ok = FALSE;
} else if ( _snd_init_buffer == 0 ) {
next_write = _snd_init_buffer++;
} else {
next_write = _snd_init_buffer++;
_snd_playing = TRUE;
_snd_next_ok = FALSE;
dmaStreamSetMemory0( SPID3.dmatx , _snd_buffer_address(0) );
dmaStreamSetMemory1( SPID3.dmatx , _snd_buffer_address(1) );
dmaStreamSetTransactionSize( SPID3.dmatx , SND_BUFSIZE );
dmaStreamEnable( SPID3.dmatx );
}
return _snd_buffer_address( next_write );
}
u8 sndGetStatus( void )
{
return _cs43l22_get( CS43L22_REG_STATUS );
}

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#ifndef __H_SOUND
#define __H_SOUND
#define SND_BUFSIZE 2304
//#define USE_DMA_FOR_SEXY_BEEPS
/* Initialise the driver at a specific audio sampling rate */
void sndInit( u32 frequency );
/* Set the driver's output volume */
void sndOutputVolume( u8 volume );
/* Get the next writeable buffer; returns NULL if all buffers are full */
s16 * sndGetBuffer( void );
/* Get the sound chip's status register */
u8 sndGetStatus( void );
#endif //__H_SOUND